1. Field of the Invention
The present invention is related to a time-delay buffer, and particularly, to a time-delay buffer having a silicide layer partially formed on the transistor gate thereof.
2. Description of the Prior Art
By their nature, logic circuit designs are timing dependent. Therein, most signals within a logic design must be synchronized with each other. However, there are instances where signals intended to be synchronized are not. For example, between two logic signals, one may be processed through a logic circuit faster than the other, and thereby the signals become non-synchronized. When this occurs, the faster of the two signals is typically time delayed so as to synchronize it with the other signal. One synchronization mechanism for implementing a time delay is known as a time delay buffer.
On a fundamental level, a timing delay buffer can be thought of as adding a predetermined amount of time delay to a circuit. In practice, a time delay buffer is generally inserted into a signal path so as to intercept a signal, add a predetermined amount of time delay to the signal, and then retransmit the time delayed signal onto the signal line. This accomplished, a faster logic signal can be time synchronized with a slower logic signal.
Conventional time delay device is formed from a chain of inverters with their inputs and outputs connected in series. FIG. 1 illustrates an example of such a timing delay device. A plurality of inverters 10 are connected in series, such that an input signal at the input terminal 12 will appear as a time delayed signal at the output 14. In this configuration of a timing delay buffer, the sum total of each inverter's delay time determines the total delay time of the series of inverters. In addition, time delay is determined by means of adjusting the width and the length of the inverters.
However, a problem occurs when the pluralities of inverters 10 connected in series are formed below the 100 nm process. That is, a number of the inverters 10 connected in series occupy a lot of space that limits the size of the time delay device. Besides, adjusting the width or the length of the channel changes the sub-threshold of the time delay device, especially the time delay device formed below the 100 nm process.